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Building ideas for Hardware design

A CPU-less AXI-Lite Debug Console: Parser and GPIO Bring-up

ASCII commands over a serial cable drive AXI-Lite registers without a CPU and bring up the first real peripheral on the bus

Posted by Nelson Campos on March 28, 2026

Building a UART Core and Turning It into an AXI-Lite Peripheral

From 8N1 framing and TX/RX FSMs to a two-register UART peripheral that any CPU or AXI-Lite master can use

Posted by Nelson Campos on March 28, 2026

Building AXI-Stream Width Converters

Upsizing, downsizing, and byte-accurate repacking for real datapaths

Posted by Nelson Campos on March 23, 2026

AXI-Stream Arbitration in SystemVerilog

Packet, beat, and weighted round-robin policies in verilaxi

Posted by Nelson Campos on March 22, 2026

AXI DMA - Moving Data Without the CPU

How DMA engines work, and building one in SystemVerilog

Posted by Nelson Campos on March 21, 2026

Synchronous and Asynchronous FIFOs in Hardware

From RTL to CDC - building reliable data buffers

Posted by Nelson Campos on March 21, 2026

Writing a CSR Block Using AXI-Lite

How control and status registers are built and wired up in hardware

Posted by Nelson Campos on March 21, 2026

SVA Protocol Checkers for AXI

Catching protocol violations early with SystemVerilog Assertions

Posted by Nelson Campos on March 21, 2026

Building SystemVerilog AXI VIP for Fast Bring-Up

Task-based AXI4 drivers for fast testbench bring-up

Posted by Nelson Campos on March 21, 2026

Reproducible RTL Simulation with Docker and GitHub Actions

No more "works on my machine"

Posted by Nelson Campos on March 21, 2026

Verilator C++ and SystemVerilog Testbench

How the simulation harness and the verification environment work together

Posted by Nelson Campos on March 21, 2026

Fixed Point Recursive FFT

Implementation of the forward and inverse FFT using hardware recursion

Posted by Nelson Campos on March 03, 2018

UVM Environment for Image Signal Processing

A Framework for Design and Verification of Image Processing Applications using UVM

Posted by Nelson Campos on November 26, 2017

Integral Image in Hardware

Convolutional Summed Area Tables for Fast Features Computation

Posted by Nelson Campos on April 02, 2017

2D Convolution in Hardware

SystemVerilog implementation of Edge Detection

Posted by Nelson Campos on December 27, 2016

A Basic Tutorial to Connect Octave with UVM

Integrating Octave into SystemC and UVM

Posted by Nelson Campos on November 26, 2016

A Basic Tutorial of UVM Connect

Integrating SystemC into UVM

Posted by Nelson Campos on October 23, 2016

A Basic Tutorial of UVM

An Introduction to Functional Verification

Posted by Nelson Campos on September 11, 2016

Hardware Synthesis

An introduction to the Synopsys Design Compiler

Posted by Nelson Campos on September 06, 2016

RGB to YCbCr conversion

Playing with bits and pixels

Posted by Nelson Campos on August 21, 2016

AMBA AXI Protocol

A brief introduction to interconnect IP blocks

Posted by Nelson Campos on August 04, 2016

Binary Logarithm

SystemVerilog implementation of the Hardware Algorithm

Posted by Nelson Campos on August 02, 2016

Square Root Computation

A Hardware Algorithm

Posted by Nelson Campos on July 28, 2016

Hardware Division

A fairly simple Algorithm

Posted by Nelson Campos on July 04, 2016

Peasant Multiplication

An overview of the Hardware Algorithm

Posted by Nelson Campos on June 26, 2016