sistenix.com


Building ideas for Hardware design

AXI DMA - Moving Data Without the CPU

How DMA engines work, and building one in SystemVerilog


Synchronous and Asynchronous FIFOs in Hardware

From RTL to CDC - building reliable data buffers


Writing a CSR Block Using AXI-Lite

How control and status registers are built and wired up in hardware


SVA Protocol Checkers for AXI

Catching protocol violations early with SystemVerilog Assertions


Building SystemVerilog AXI VIP for Fast Bring-Up

Task-based AXI4 drivers for fast testbench bring-up


Reproducible RTL Simulation with Docker and GitHub Actions

No more "works on my machine"


Verilator C++ and SystemVerilog Testbench

How the simulation harness and the verification environment work together


Fixed Point Recursive FFT

Implementation of the forward and inverse FFT using hardware recursion


UVM Environment for Image Signal Processing

A Framework for Design and Verification of Image Processing Applications using UVM


Integral Image in Hardware

Convolutional Summed Area Tables for Fast Features Computation


2D Convolution in Hardware

SystemVerilog implementation of Edge Detection


A Basic Tutorial to Connect Octave with UVM

Integrating Octave into SystemC and UVM


A Basic Tutorial of UVM Connect

Integrating SystemC into UVM


A Basic Tutorial of UVM

An Introduction to Functional Verification


Hardware Synthesis

An introduction to the Synopsys Design Compiler


RGB to YCbCr conversion

Playing with bits and pixels


AMBA AXI Protocol

A brief introduction to interconnect IP blocks


Binary Logarithm

SystemVerilog implementation of the Hardware Algorithm


Square Root Computation

A Hardware Algorithm


Hardware Division

A fairly simple Algorithm


Peasant Multiplication

An overview of the Hardware Algorithm